Laminated Busbar: The "Parasitic Inductance Killer" for SiC High?Frequency & High?Voltage Systems — Why Is It Mandatory for Low?Parasitic Packaging?

Laminated Busbar: The "Parasitic Inductance Killer" for SiC High‑Frequency & High‑Voltage Systems — Why Is It Mandatory for Low‑Parasitic Packaging?

In the packaging design of SiC power modules, there is one component frequently mentioned yet easily underestimated: the laminated busbar. As SiC MOSFET switching speed exceeds 100 kV/μs and DC‑bus voltage rises to 800 V and above, the parasitic inductance introduced by conventional cables or discrete copper busbars becomes a “hidden reliability bomb” for power systems. Within STMicroelectronics’ low‑parasitic SiC packaging solution, laminated busbars are one of the key enablers that reduce loop inductance from 6.6 nH down to 4.61 nH.

Drawing on ST’s packaging analysis, this article elaborates on the intrinsic link between laminated busbars and low‑parasitic design: how they resolve critical pain‑points of high‑frequency SiC systems, and which key parameters must be well‑controlled during design.

I. The “Speed Advantage” of SiC Turns Conventional Busbars into Bottlenecks

The superior high‑frequency performance of SiC devices is double‑edged. Compared with equivalent IGBTs, SiC achieves 30%‑50% lower switching losses. Nevertheless, high di/dt (rate of current change) amplifies the adverse impact of parasitic inductance exponentially.

ST’s turn‑off over‑voltage formula:

At DC‑bus voltage VBUS=860V and di/dt = 18.9 A/ns, every 1 nH of extra parasitic inductance contributes 18.9 V of voltage overshoot. With busbar parasitic inductance reaching 10 nH, the overshoot increases by 189 V. This not only erodes the device voltage derating margin but also aggravates ringing and EMI issues.

Traditional busbars adopt discrete positive/negative copper bars or long cable interconnections. The large physical separation between forward and return current paths creates huge loop area, yielding parasitic inductance in the range of 20‑100 nH, which cannot satisfy high‑frequency SiC requirements. For ST’s double‑sided cooling module optimization, enlarging the busbar area is a core measure. Fundamentally, laminated structures shrink loop area to mitigate parasitic inductance at source.

II. Inductance‑Reduction Mechanism of Laminated Busbars: Magnetic‑Field Cancellation

The core principle of laminated busbars is tight‑coupling of forward and return current layers, leveraging magnetic‑field cancellation to reduce overall inductance.

According to ST’s comparative tests: when positive and negative copper layers are stacked in parallel with a thin dielectric interlayer, magnetic fields generated by forward and reverse currents partially cancel each other. Parasitic inductance can be reduced to several nH, achieving more than 60% inductance reduction versus discrete layouts.

This inductance‑reduction effect follows geometric rules for parasitic parameters:

The smaller the distance between conductor and reference plane, the smaller the loop area, and the lower the parasitic inductance.

By stacking positive and negative conductors together, laminated busbars compress bulky 3‑D current loops into planar tightly‑coupled structures. Copper width and dielectric thickness can be further optimized to balance inductance and parasitic capacitance. This represents a typical example of “geometry‑parasitic co‑optimization” in ST’s low‑parasitic packaging.

III. Laminated Busbar Design: Stacking Alone Is Not Sufficient — Three Critical Parameters

According to ST simulation and test results, laminated busbar optimization must consider overall packaging layout. Three key parameters are highlighted below:

1. Dielectric layer thickness: minimize thickness while meeting voltage withstand requirements

The dielectric layer separates positive and negative conductors and defines coupling distance. Per ST’s geometric rules, thinner dielectrics bring closer conductor spacing and lower inductance. However, dielectric thickness must comply with system voltage rating. For 800 V systems, polyimide or epoxy dielectric of minimum 0.2 mm thickness is recommended to avoid partial discharge.

2. Copper bar width and loop symmetry

In ST’s optimization case, enlarged busbar area reduces inductance by shortening equivalent current path and improving symmetry between upper‑arm and lower‑arm loops, thus preventing excessive local current density. Insufficient copper width leads to edge‑crowded current distribution, raising both inductance and conduction resistance. In ST’s benchmark, loop resistance drops from 134.9 μΩ to 99.3 μΩ, where wider copper contributes over 30% of the total improvement.

3. Interconnection distance to power chips

The interconnection length between laminated busbar terminals and module power terminals strongly dominates total parasitic performance. In ST’s solution, laminated busbars are soldered directly onto DBC power terminals, eliminating long intermediate cables. The “busbar‑terminal‑chip” current loop is further compressed, enabling total loop inductance down to 4.61 nH.

IV. Laminated Busbar Must Be Integrated into Packaging Simulation Closed‑Loop

From ST low‑parasitic design methodology, laminated busbars cannot be designed in isolation. They must be simulated together with chip layout, bond‑wire / copper‑clip interconnections and DBC substrates:

1. Apply FEM (Finite‑Element Method) to extract busbar parasitic inductance and resistance; identify hot‑spots via current‑density contour plots.
2. Import extracted busbar parasitics into SPICE models to simulate turn‑off overshoot, ringing and switching losses.
3. Evaluate alternative structures (lamination thickness, copper geometry) and select the optimal solution.

This “structure‑simulation‑validation” closed‑loop workflow avoids the conventional practice where busbars are fitted as an afterthought, ensuring busbar performance aligns with system‑level parasitic targets.

V. Future Trends of Laminated Busbars Based on ST Practices

ST’s double‑sided‑cooled modules have proven the value of laminated busbars. Driven by higher power‑density requirements, three development directions emerge:

1. Integration: Integrate laminated busbar with DC‑link capacitors and driver circuits to shorten power loops. For instance, embedding DC‑link capacitors inside busbar dielectric layers eliminates the “last mile” of bus inductance.
2. Thin‑profile design: Adopt ultra‑thin dielectrics and copper foils, catering to vertical short‑loop requirements of 3D‑packaging and embedded packaging.
3. Material upgrade: Replace conventional soldering with silver sintering for busbar‑terminal joints, lowering contact resistance and improving thermal conductivity for high‑power SiC modules.

Conclusion

For high‑frequency high‑voltage SiC systems, laminated busbars are no longer optional accessories but core building‑blocks for low‑parasitic packaging. Beyond inductance reduction, tightly‑coupled‑loop design extends geometric optimization from chip‑level to system‑level. As emphasized in ST technical materials: low‑parasitic packaging requires holistic optimization covering geometry, interconnection, busbar and simulation — and laminated busbar acts as the critical bridge connecting chips and power systems.

As SiC modules evolve toward 1200 V, 2000 V and beyond, laminated busbar design accuracy directly determines system reliability boundaries. Tighter control over busbar parasitic parameters brings competitive advantages in SiC system development.

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